Embedded NVM adds flexibility to power management designs

Toward a more logical NVM
While today's designers have numerous NVM options, the field narrows to those that can be embedded at low cost, and yet also exhibit high performance and application flexibility. For certain applications, those objectives rule out a number of possibilities. For example, while traditional laser fuses may be appropriate for bits in the single digits, they are one-time factory programmable. Forget about iterative precision analog trim, forget about field upgrades, and forget about reliability—the many shortcomings of poly fuses are well documented and well known. A better option is Flash, but then you can forget about low cost; the process adders required to fabricate this NVM architecture run into the hundreds of dollars per wafer. EEPROM, on the other hand, has been around for quite some time. As such, it is relatively inexpensive… but not when you consider that it is limited to older process technologies, which also limit performance to unacceptably low levels. As for the newer breeds of embedded EEPROM, which, like Flash, require additional mask layers and process steps, you can erase the cost advantages of the previous generation technology.

The solution that many players in critical hot markets have turned to is NVM designed in Logic CMOS. Not only is it compatible with the straight CMOS process objectives of hot market applications like power management, Logic CMOS's powerful combination of high-performance and low cost make it ideally suited to embedded NVM.

Power management options and tradeoffs
With the advances in semiconductor process technology that enable tremendously high levels of integration and low voltage operation come particular challenges in managing the power supplied to these chips. For the high-performance microprocessors, current requirements are escalating at an exponential rate, pushed even further by faster and faster clock rates. With processor current surges well in excess of 100 A, the need for accurate, low-noise power, combined with the need for flexible control over power delivery, has become a principal concern for both chip-level and system-level design.

For the designer of power management ICs, though, cost has become a principal concern. As it turns out there is a sweet spot where the design architecture, die size, and process technology considerations converge to compel the cost-saving integration of small bit-count NVM (typically less than 512 bytes). In the case of power management ICs, older process technologies (0.35μm for example) are certainly the lowest cost, but they are also commensurately lower in performance and lack the cutting-edge library and intellectual property (IP) availability that enables competitive differentiation. As such, they cannot meet aggressive and innovative design objectives. On the other end of the spectrum are the leading-edge process technologies (90 nm down to 60 nm). While they have a place in very specific applications, these processes are very costly, to say nothing of the fact that near-term design schedules targeted to these processes will require the simultaneous risk qualification of essential cell library elements. Because the resulting cost and potential hits to market delivery times, they best remain, for the moment, on the drawing board for most application segments. Logic CMOS processes in 0.25μm (and down to 0.18μm and 0.13μm), on the other hand, easily satisfy cost, performance, and library availability objectives of power management IC designs. These technologies are simultaneously advanced and stable. What’s more, their ubiquity translates to competitive cost, and equally important, the availability of proven, qualified (or soon to be qualified) advanced NVM blocks.

Regarding the design architecture side of the equation, NVM has become such an attractive element for the trimming of reference voltages and currents, amplifier offsets, and other analog parameters, that its use has been virtually mandated by the emerging PMBus (Power Management Bus) standard. By virtue of this new digital power management communications protocol, PMBus commands are used to set a power supply's operating parameters (via programming of the NVM), monitor operation, and also execute corrective operations in response to faults. The implications for small bit-count NVM in this scenario should be obvious to even the casual observer! Default channel voltages, direction and type of pull-ups and pull-downs, the characteristics of the various GPIOs, voltage ramp times, turn-on and turn-off sequences—all are parameters whose configurable values are efficiently and conveniently stored in embedded NVM.

Driven by the need for precise calibration of digital voltage regulation and conversion circuits, the requisite values are best written during production test into the small, on-chip NVM. Not only can the entire memory be programmed and tested at this point, the specific configuration settings stored in the NVM can be verified at the same time, greatly enhancing the final test yield for the power management module. Finally, firmware patches are also greatly served by the contents of the NVM when the product is upgraded or reconfigured in the field.

Conclusion
Serving critical functions ranging from pre- and post-production analog trim to upgrading fielded product, multiple-times programmable NVM enables not only innovation, but practical utility. Its application in hot markets like power management means that manufacturers are able to reprogram devices multiple times in the course of the development cycle, which contributes the agility needed to respond to fast-changing market demands, to say nothing of streamlining manufacturing operations, fine-tuning performance, and correcting problems remotely in the field.

With availability in a number of application-optimized architectures, and in configurations from 16 bits to 256K bits (with numerous functional options), Impinj has an embedded AEON NVM solution suited to improving the cost, performance, functionality, security, reliability, and time-to-market requirements of power management applications. And by virtue of being targeted to advanced generic CMOS processes, AEON NVM requires no additional mask layers or processing steps (unlike Flash or EEPROM), and, unlike OTP/poly fuse solutions, it is multiple-times programmable.

About the authors
Larry Morrell, Vice President IP Products at Impinj, Inc. has over 20 years of semiconductor-industry experience in engineering, management, and marketing roles. In his current role, Mr. Morrell oversees engineering, sales, marketing and operations for the IP licensing business at Impinj. Previously, he directed marketing for Cypress' programmable clocks division and launched their market-leading USB chip business. Prior to Cypress, Mr. Morrell was the Vice President of Marketing and Business Development for Data I/O where he helped popularize FPGAs and co-founded an industry tradeshow. He established a European sales and marketing operation in Paris for IC startup, Seattle Silicon, and worked in engineering and management at Boeing. Mr. Morrell was founder of the Madronanet Corporation, which provided executive coaching and career management services, and owner of the recruiting firm, IC Recruiting, specializing in placing engineers and executives in the IC industry. Mr. Morrell earned a B.S. in Computer and Electrical Engineering and a B.A. in Russian Languages from New Mexico State University. Larry’s email address is larry.morrell@impinj.com

Semiconductor veteran Deepak Savadatti is currently the Vice President of Marketing for California-based Primarion, a mixed-signal semiconductor company that provides digital control of power and I/O solutions. Experienced in both established and developmental phase start-up companies, Savadatti has a varied background in product management, marketing and sales. Previously, as the director of offline products at leading digital power management company iWatt, he was responsible for driving all sales, product marketing, and engineering efforts in a start-up environment. Savadatti has also held prior managerial roles at Hifn, a network security and flow classification market leader, and at Quality Semiconductor and California Micro Devices. Savadatti earned his Bachelor’s degree in electronics and communication engineering from Karnataka University (India) and his Master’s degree in electrical and computer engineering at Okalahoma State University. His e-mail address is deepak.savadatti.com.

John Schroeter, Senior Manager, Marketing Communications, is responsible for technical and product marketing communications at Impinj, Inc. Prior to joining Impinj, he held product and strategic marketing management posts at UTMC, Seattle Silicon, and Fairchild Semiconductor’s Memory & High-Speed Logic division. He is the author of the Prentice Hall book, Surviving the ASIC Experience. John’s email address is john.schroeter@impinj.com.

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