Power Reduction Techniques in Mixed-Signal Integrated Circuits: Practical Approaches

To address these issues, one established way to reduce IC power consumption is to have areas of an IC built using different process technologies, mainly oxide thicknesses or Complementary Metal-Oxide Semiconductor (CMOS)/Bipolar+CMOS (BICMOS) combinations, by selecting the supply voltages relative to the operating frequencies.

It turns out that this is no cure-all either. By doing this, one now requires multiple power supplies for the IC. One way around to this is to have a single IC supply voltage and generate lower voltage supplies within the IC itself.

IDT authors discuss the trade-offs and considerations for obtaining the lowest power in various cases. The entire technical paper can be read here.

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