Top 10 methods for ASIC power minimization -- Part 1

The physical limits of CMOS technology scaling and the ever increasing number of on-chip features is causing low power design to move from being one of many design metrics to being the number one design metric. Some authors have written "doom and gloom papers" proclaiming the end of Moore's law due to the inability to scale down power as we move to 65 nm and below. While there is some truth to this, a counter claim could be made that that the VLSI design community is still lagging in its application of low power design techniques and that the fundamental show stopper is still a ways out. Considering that many of the low power techniques that are starting to be employed today were invented 10 to 20 years ago, there is still plenty of space at the bottom. The goal of this article is to summarize the most effective low power techniques available today and to highlight some of the challenges that lie ahead.

1. Understand the power requirements of the system
Although it may seem obvious, the most important step to reducing ASIC power is to understand the final system application. With a thorough understanding of the end system, designers and chip architects can set realistic goals for the processor power budget and define the low-power techniques that are suitable for the processor. Before any low-power design effort can be started, a slew of questions need to be answered by the design team. Is the system a battery-operated system or stationary system? In battery-operated systems, the energy consumption is what really matters, while in stationary systems the thermal budget and cooling costs generally dictate the power budget. Does the system require real-time processing, or can delays vary according to the thermal load of the system? At the board level, are there restrictions on the number of power supplies that can be used or on the power-management features that can be employed? How sophisticated are the power management circuits employed by the system? What is the system power budget in relation to the chip budget? If the power of the circuit in question is only a fraction of the total system power, does it make sense to employ aggressive power saving techniques? Does the power minimization have to be handled completely in hardware or can it be managed through software? How much wakeup latency is acceptable when waking up from standby states? Finally, what is the power budget of the system, how flexible is it, and under what processing was it specified? Unless all of these questions can be answered up front, there is little chance that the project will be a low-power success story.

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