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While current-mode control (CMC) remains the much preferred PWM scheme for switchmode power supplies, its advantages aren't automatic. Indeed, ensuring stability in a switchmode supply involves such factors as the right type of slope compensation, a subject that's not too easy to grasp without a cadre of mathematical formulae that, although necessary to successful modeling and design, more often than not keeps the typical system designer from appreciating the underlying issues. We address that issue in this article by turning to graphical representations derived from the basic CMC circuit equations to provide you with an intuitive understanding of what proper CMC and slope-compensation design are all about.
Overview
The primary advantage of CMC is simplified system-loop compensation. In the very simplest form, a single compensation capacitor, Co, and resistor, Ro, are selected that cancel the predictable pole created by the RC pair. The resultant loop acts as a single-pole system. Also, line regulation is inherently better, as is immunity from audio effects.
But there's more to it. For PWM duty cycles above 50 percent, all current-mode control buck converters require a linear ramp (i.e., slope-compensation) to avoid sub-harmonic oscillation. And higher duty cycles require greater slope compensation. Using nonlinear compensation circuitry (such as found in National's LM20xxx series, for instance) offers a better solution because it optimizes the stability of the regulator device over the entire output voltage range.
Basic current-mode operation
In the typical fixed-frequency DC/DC converter, a PWM pulse controls the time during which the inductor is energized within each switch period. CMC, in the simplest terms, compares a slow moving output-voltage error signal to the relatively fast changing inductor current. The inductor current sense signal can be converted to a 'sense' voltage signal for a voltage comparator based CMC design, a method commonly described in the literature. Alternatively, the error signal can also be converted to a current so that the regulator's three signal currents (error or control, current sense, and slope compensation) can be summed at a common node for comparison. The two approaches are equivalent. Let's look at current-summing as shown in Fig. 1, which illustrates the entire control loop for a CMC buck DC/DC converter.
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Fig. 1: Current-mode buck converter, CMC loop highlighted
The CMC circuitry is highlighted in red. The RS flip-flop is central to the CMC timing. A fixed frequency clock sets the flip-flop, which then turns on the power FET and energizes the inductor. This is the start of the PWM pulse. A current-sense feedback signal terminates the PWM when the energizing current in the inductor, reflected to the summing node via the sense circuit, reaches a peak control level, Icontrol - Islope.
Icontrol is directly related to the Vout error signal, Vc. During the PWM 'on' pulse time, the power FET conducts and inductor current increases. The rate of increase for the inductor current during this period is defined as Su. It's controlled by the difference between Vin and Vout, the voltage drop in the FET switch, and the value of the inductor, L. More specifically, Su increases with increasing (Vin - Vout) and decreases with increasing L. When the PWM pulse is terminated and the FET turns off, inductor current flows from the diode. The inductor current decreases linearly until the next cycle.
The rate of inductor current change during this 'off' time is defined as Sd. The waveform diagrams that follow assume the voltage drop in the FET switch and the diode has negligible effect on the shape of the waveforms. The diode is often replaced with a low-loss synchronous FET switch.
A p-channel MOSFET is used in this circuit, but the switch could be an n-channel MOSFET. In the steady state condition, the starting and ending inductor currents within a switching period, Ts, are identical. The average inductor current is the DC/DC converter load current.
Only the peak inductor current needs to be sensed. For this reason sensing the current in the power FET is equally effective as sensing the actual inductor current. Isense is typically 10 micoamps to 100 microamps per ampere of inductor current.
Current-mode control is desirable because the CMC loop in effect forces the peak current to be the same for each switch cycle as long as Vc is constant. Thus, the inductor in combination with the CMC loop can be thought of as a current source. Unlike voltage-mode control, the inductor L and output filter capacitor, Co, do not contribute a complex pole pair to the overall system loop. The removal of a power pole due to L in the CMC system loop removes the need for a corresponding zero in the overall system compensation network. A single RC network is adequate for optimal CMC system compensation, a significant reduction in complexity for tuning system performance.
The non-CMC portion of the system loop, highlighted in Fig. 2, generates the control voltage, Vc. In operation, this "outside" loop regulates Vout by providing the control signal to the CMC circuitry. In turn, the CMC provides the PWM value that generates the desired output voltage, which in turn satisfies the requirement for balance at the error amplifier's input.
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Fig. 2: Buck converter, voltage regulation loop highlighted
Now consider the basic summing node signals at the core of the CMC loop (Fig. 3). The waveforms shown at the summing node excludes the slope compensation current, Islope. Isense is representative of the inductor current during PWM high, and returns to zero once Isense exceeds Icontrol and the PWM is terminated.
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Fig. 3: CMC summing node without slope compensation
The peak current in the inductor is limited by the Icontrol signal, which is directly controlled by the output of the error signal, Vc. The CMC also requires the addition of Islope to the control signal. This additional signal is shown in Fig. 4.
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Fig. 4: CMC summing node with slope compensation
The effect of Islope is to modify the slow moving Icontrol signal so that it has a downward slope for the duration of each switching cycle. Notice the change of the two summing node waveforms with the addition of Islope. This example illustrates a nonlinear Islope signal. Islope is often a sawtooth waveform with linear ramp. But as we will see, there's a great difference between linear and nonlinear slope compensation.
Evaluating the transient responses
What role does Islope play in the operation of the CMC loop? To find out, let's observe
the settling of the inductor current loop in response to a theoretical disruption of the inductor current.
The loop's recovery to a hypothetical disruption in inductor current, under certain regions of CMC operation, can take excessive time to settle. Sometimes, settling is never achieved and the circuit falls into the sub-harmonic oscillation seen in improperly compensated CMC circuits.
The first three sets of plots in Figs. 5-7 show current settling for duty cycles of 25, 50, and 66 percent, respectively, for a CMC loop that has no Islope. In each case the load current or average inductor current is arbitrarily selected to be 2.5 amps and the inductor ripple current is adjusted to be 30 percent of the load current. The desired value of switching frequency, duty cycle, Vout, and ripple current specify the value of inductor for each case. These three examples represent the same control circuit and input supply operating with three different feedback attenuation resistor settings that provide three different values of Vout.
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Fig. 5: Perturbed inductor current; duty cycle = 25, Islope = 0.
See Fig. 5. For all the waveforms in this section, the green dashed triangle waveform is the expected steady state inductor current for the specific application's duty cycle. The duty cycle is 25 percent; therefore the power FET is conducting energizing current from Vin to the load via the inductor for approximately the first 25 percent of each switching cycle.
The solid black lines are the CMC control currents referenced to the inductor current. The control current determines the peak value of the sensed inductor current, so it is convenient to refer the control signal to the level of the inductor current in order to plot the two signals on the same scale. The third (solid red) waveform is a hypothetical perturbed inductor current which at time t=0 is one half of the steady state inductor current. The perturbed inductor current is still constrained by Vin and Vout to have 'on' and 'off' period slopes of Su and Sd. For 25 percent duty cycle, the perturbation to the inductor current is able to converge to the desired steady state pattern within several switching cycles.
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