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Nonisolated DC/DC step-down voltage conversion is almost exclusively based on the ubiquitous buck regulator topology. The multiphase buck regulator has inherent advantages over its single-phase counterpart and is a suitable candidate in many applications, given the trend towards lower supply voltages and greater load-current requirements. Multiphase interleaved circuits are commonly found in VRMs for computing and server applications where high output current and fast transient response is crucial. However, the scheme may also have some merit in lower current applications where profile or thermal performance is critical.
The fundamental limitation of the conventional single-phase buck converter is the tradeoff of efficiency and switching frequency. Output ripple and dynamic response improve with increased switching frequency. The physical size and value of the filter inductor and capacitors become smaller at higher switching frequencies. There is, however, a practical limitation to the switching frequency: switching losses increase with frequency, and resulting efficiency tends to be lower.
The multiphase interleaved buck topology offers a solution to this conundrum. The fundamental frequency is effectively multiplied by the number of phases used, improving transient response. Other intrinsic advantages of this solution include reduced input and output capacitor RMS currents; reduced EMI filtering requirements; the option to combine multiple filter inductors into one integrated magnetic device; lower profile and decreased PCB real estate solution size; better thermal and forced convection performance; improved reliability and power stage redundancy; and easier power train component selection. We discuss these advantages and provide an example of a two-phase integrated FET buck converter design.
Multiphase interleaved converter
The power train schematic of an interleaved multiphase buck converter implementation with N phases is shown in Fig. 1. The output voltage and output current are denoted Vo and Io, respectively. Ideal components are shown and component parasitics such as inductor DCR and capacitor ESR and ESL are not represented. The switches are shown implemented using n-channel high-side and low-side MOSFETs, denoted by QT1, QT2,..., QTN and QB1, QB2,..., QBN, respectively. The high-side switches are driven at a duty cycle ratio D, where:
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 Eq. 1
The low-side switches are driven in complementary fashion at duty cycle 1-D. All switches operate at constant switching frequency, fs = 1/Ts, where Ts is the switching period. The oscillators are synchronized such that each phase is driven by gate drive signals of the same switching frequency fs but adjacent phases are phase shifted by 360°C/N. For example, a three-phase converter is driven by gate signals at 0, 120, and 240 degrees. The input and output of each buck cell are paralleled such that the fundamental ripple frequency at the input and output is Nfs.
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Fig. 1: N-phase interleaved multiphase buck converter, synchronous rectification
The output filter consists of inductive elements Lf = Lf1 = Lf2 = = LfN and capacitance Co; Cin denotes the input filter capacitance. Input and output capacitor currents are iCin(t) and iCout(t), respectively, with polarity as indicated. Note that the filter inductors are represented as separate elements in each phase whereas the input and output capacitors are shared. Assuming ideal current sharing due to interleaving, we can write:
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 Eq. 2
The various circuit current waveforms are shown in Figs. 2a and 2b for a three-phase buck converter running at 500 kHz. Each phase is phase-shifted by 120 degrees from its adjacent phase. The DC output current of each phase, i.e., Io1, Io2, Io3, is 1 amp such that total DC output current, Io, is 3 amps. Each phase operates at 50 percent duty cycle.
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Fig. 2: Three-phase buck converter waveforms: inductor phase currents (top); buck switch currents (bottom)
Inductor Ripple Current
Given the per-phase inductors have equal inductance value and experience equal applied volt-seconds, then the inductor ripple currents are equal. The peak-to-peak inductor ripple current, ΔiL, is given by Eq. 3, where ILmax and ILmin are the peak and valley currents, respectively.
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 Eq. 3
The net output ripple current of the multiphase buck flows into the output capacitor as expressed by Eq. 4, where m = floor(N•D) and the floor function returns the greatest integer value less than the argument.
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 Eq. 4
For example, if D < 1/N, m = 0 and Eq. 4 simplifies to
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 Eq. 5
This term is smaller than the individual inductor ripple current given by Eq. 3 due to current cancellation of the interleaved buck cells.
Input Capacitor
Neglecting inductor ripple current, the input capacitor of the single-phase buck converter sources current Io - Iin during the D interval as the high-side switch conducts. The capacitor is charged by current of amplitude Iin during the 1-D interval when the low-side switch conducts. Thus, the single-phase buck input capacitor conducts a square-wave current of peak-to-peak amplitude Io and the capacitive component of AC ripple voltage is a triangular waveform. The resultant input capacitor RMS current is:
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 Eq. 6
In the multiphase buck, the per-phase input currents are interleaved and overlap occurs if D > 1/N. Figure 3a shows the 500 kHz per-phase input-capacitor current components for a three-phase buck converter. These components are aggregated to calculate the instantaneous 1.5 MHz current flowing in the input capacitor, shown in Fig. 3b. For comparison, the capacitor current of a similar power single-phase topology is shown in Fig. 3c. Again, duty cycle is 50 percent.
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Fig. 3: Input capacitor currents: (a) per-phase capacitor current constituent components; (b) effective input capacitor current (1.5 MHz) of a three-phase converter; (c) input capacitor current of a single-phase (500 kHz) buck converter
The corresponding multiphase input-capacitor RMS current is expressed by Eq. 7:
(Click on Equation to Enlarge)
 Eq. 7
Figure 4 shows a plot of normalized input-capacitor RMS current for one up to four interleaved phases. The result is normalized to unity current, Io = 1 amp, and per-phase ripple current amplitude, ΔiL, is set at 30 percent of the per-phase DC current, Io/N. By examination, we note that the ICin,rms minima appear at critical duty cycles given by Eq. 8.
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 Eq. 8
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Fig. 4: Normalized input capacitor RMS current, multiphase converter, N = 1, 2, 3, 4
If we take the ratio of Eq. 6 to Eq. 7, we can quantify the input-capacitor RMS current attenuation factor for an N-phase buck converter. This parameter is plotted in Fig. 5.
If the duty cycle is known for a certain application or where there is little expected input voltage variation, it is possible for us to choose N with reference to Eq. 8 such that the input-capacitor RMS current is substantially eliminated. Accordingly, we can define a high-current multiphase buck regulator with dramatically reduced input-capacitor cost, size, profile, and PCB area. In any case, the multiphase input- capacitor current amplitude is greatly reduced relative to that of the single-phase connection. The reduced current, in tandem with higher effective ripple frequency, enables a lower value capacitance for a given input AC ripple voltage specification.
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Fig. 5: Input capacitor RMS current attenuation factor, multiphase buck converter
The input capacitor's ESR power dissipation is given by Eq. 9, with ICin,rms defined by Eq. 7.
(Click on Equation to Enlarge)
 Eq. 9
Thus, power dissipation in the multiphase input capacitor ESR is reduced, thereby alleviating capacitor self-heating and extending capacitor lifetime. Moreover, high current slew rates and correlated EMI are minimized and, given the higher fundamental ripple frequency, the input EMI noise filter will be smaller and less expensive.
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