SANTA CLARA, Calif. — Design engineers debated the practical uses of controlled equivalent series resistance bypass capacitors at an evening panel discussion during DesignCon here Monday (Jan. 29).
The stage for the discussion was set at an earlier TechForum, where Istvan Novak, senior signal integrity staff engineer at Sun Microsystems, said, "One of the most heated debates in the SI [signal integrity] community concerns the optimum and proper ESR value of bypass capacitors." Novak claimed that today controlled ESR bulk and ceramic capacitors are becoming available. He presented three controlled ESR options from capacitor providers Sanyo, Kemet and TDK.
When buying electrolytic capacitors, design engineers are giving increasing importance to ESR, in addition to voltage, capacitance, operating temperature and price, according to industry observers. As a result, the low-ESR market continues to be one of the fastest growth sectors in the global capacitor industry. Price, however, continues to be the most important criterion, regardless of how fast the capacitor releases its charge.
Lowering the ESR increases the speed at which the capacitor can release its charge. This speed is important for decoupling microprocessors. Single-digit ESR is the near term-target, with most designers envisioning ESR ratings of less than 1.
"We ship a server every 14 seconds 24/7, and we need to have consistent optimized designs across our family of products," said Terry Morris, a fellow at Hewlett-Packard. "It used to be OK to just perform transient analysis on our designs; now we need to sharpen our pencils."
The "sharpening" to which Morris referred is the strategic placement of ESR capacitors on the die, in the IC package and on the PC board. The aim is to minimize transients in designs, from power sources in vehicle applications to audio amplifiers in HDTVs.
When thinking about using ESR capacitors in high-speed serial designs, however, engineers find they need to place them judiciously in order to minimize inductive loops at the on-die, on-package and on-board levels.
"There are constant design trade-offs for using ESR capacitors as decoupling devices," said IBM Corp. distinguished engineer Bruce Archambeault. "When you need charge delivery, you need to place it close to the IC. When controlling resonance, you need to distribute them across the board at strategic locations."
Archambeault said that designers need to calculate the connection inductance not only at the local level but also at the system level, and keep that between 1 and 5 nanohenrys for the appropriate ESR.
Senior hardware engineers Jorge Rodriguez from Intel Corp. and Alex Waizman from Nvidia Corp. teamed up for a presentation in which they called for industry and capacitor vendors to agree to use a limited number of ESR electrolytic levels in designs. The two had worked together previously at Intel. "When Alex came to me seven years ago and said he had the need for ESR capacitors in his designs, I laughed at him," said Rodriguez. "It's no longer a laughing matter with today's tight tolerances and high speeds in crammed spaces."
Today Waizman focuses on chip set and graphics processor packaging. Prior to joining Nvidia, he was a senior principal engineer at Intel Israel, responsible for the implementation of the Intel Centrino, Core Duo and Core2 Duo processor platforms. "The ESR of a decoupling capacitor should be the same as the ESR of the bulk capacitance of the circuit," said Waizman.
Rodriguez referred to a 2000 paper delivered by Waizman on a patented extended adaptive voltage-positioning methodology that has become more and more relevant in today's designs. EAVP is a robust methodology that is used for the design and analysis of a low-impedance resonant-free power delivery network. It utilizes and extends the theory of adaptive voltage positioning that is commonly used in voltage regulator module design and operation.
Using EAVP, uncertainties in the design guardband noise budget can be removed, resulting in significant performance improvement and cost reduction. "Design optimization of decoupling capacitors with EAVP can do wonders to a design," said Rodriguez.
