As power has become more expensive in electronic systems, the need to specify low power design intent has increased in importance. Whereas dynamic power (aka, switching) is fairly well handled using existing design and verification tools and methods, management of static power consumption (aka, leakage) requires the use of new design techniques that fall outside the capabilities of existing HDLs. If HDLs cannot capture the low power design intent, then verification tools can neither simulate nor prove that the low power design intent is correct. Also, implementation tools require proprietary mechanisms so that users can provide the necessary information to create the low power chip.
The EDA industry responded with various ways to augment logic design with low power formats. However, the lack of a single, standard format resulted in costly inefficiencies and an error-prone process resulting form the need to rewrite the low power specification for each tool in the design and verification flow, severely impacting productivity, profit margin, and design quality.
For this reason, Accellera, at the request and assistance of end users and with technical donations and contributions from multiple EDA vendors, developed the Unified Power Format (UPF) to capture low power design intent in a portable and interoperable form that can be used with most design verification and implementation tools throughout the design flow.
Written in tcl, UPF captures the low power design specification for use throughout the RTL to GDSII flow applying consistent semantics for both verification and implementation. Figure 1 shows how a UPF side file augments the HDL code to form a complete design specification at any level of abstraction. Because it is separate from the HDL description and can be read by all of the tools in the flow, the UPF side file is as portable and interoperable as the logic design's HDL code.
1. The UPF side file provides a consistent semantic for all tools throughout the design flow.
Defining System Power States and the Supply Network
When designing the low power aspects of an electronic system, you should start by defining the system power states. For example, a system power state may be such that the modem is in sentinel mode, waiting for an incoming call; the information management system is checking for scheduled appointments; and the rest of the system is in sleep mode to conserve power.
Such a deep sleep state must be defined in terms of the functionality in the system. The UPF provides two commands for defining a power state table, which captures the system power state information.
2. This is an example of a system power state table.
Create_pst defines the name of the table and its columns — the supply nets or ports that are the terms by which a state is defined. Add_pst_state defines the rows of the power state table. The power state table defines the power states in terms of the supply net states, ensuring integration of the system power design with the low power design implementation. The UPF also allows you to specify all the supply network information needed to verify and implement the power supply distribution and control required to realize the system power states.
The supply network consists of the following components and their related UPF commands:
- Power switches created with the create_power_switch command.
- Supply ports, which are defined for power domains (discussed next) and power switches. The create_supply_port command creates a port on a power domain (they are defined for switches in the create_power_switch command).
- Supply nets are created with create_supply_net. Supply nets connect supply ports and logic ports that propagate the supply state (on, off, and voltage value). The connect_supply_net command connects supply nets to one or more ports.
- Supply states. Each supply port has one or more supply state defined. The port may drive only one state at any given time. That state is propagated by the supply net connected to the port. The power state table is defined in terms of these states.
If the design is completely PG (power and ground supply) connected, then no additional work is required. However, the specification of a fully PG connected design is a laborious task. UPF automates the connection of the supply network to the logic elements in the design.
