|
The semiconductor industry's eternal mantra "smaller is better" is runnning into trouble with power issues as feature sizes continue to shrink. Complementary metal oxide semiconductor (CMOS) process technology is the dominant approach for modern microprocessor and digital signal processor (DSP) products. But as CMOS fabrication process technologies migrate from 90 nm to 65 nm and below and chip densities increase, static and dynamic power consumption often rise above acceptable levels. Apply voltage-scaling techniques to manage both.
Managing tradeoffs
Following Moore's Law, chip-level transistor densities and chip complexity double about every 24 months and the performance of integrated circuits increases proportionally. There's greater integration for more functionality in the same or less area and additional features and higher speeds at lower cost.
As much as any other type of chip to benefit from Moore's Law, DSPs have enabled a slew of new multimedia applications such as portable media players, smartphones, and rich imaging devices. At the same time, infrastructure applications in telecommunications, wireless communications and networking have benefited tremendously.
CMOS technology is commonly used for modern DSP and microprocessor designs. Compared to others, this technology is easier to process and scale. In addition, it offers a good performance-to-power-consumption ratio.
But while scaling of advanced technologies enables more elements and functionality per area, the power-per-area (power density) also increases. As steady silicon technology development pushes CMOS below the 65-nm process technology node to even smaller structure sizes, the issue of chip-level static and dynamic power takes on greater importance.
Static power consumption is power that is dissipated when the device is powered-up, but idle, i.e., there is no transistor switching activity. Thus, static power consumption is independent of workload and any usage scenario. The main component of static power consumption is leakage current, IL, which is mostly affected by transistor type including physical dimensions (width, length) and various characteristics of the silicon fabrication process technology (e.g., oxide thickness, doping profile).
At the transistor level, the static power consumption, PS, is the product of the supply voltage, Vss, and IL. Contributors to leakage current are the sub threshold leakage (I) while the transistor is switched off; the junction leakage (IL,J); and the tunneling leakage (IL,GT). See Fig. 1.
Figure 1: NMOS transistor cell with leakage currents
The dynamic power consumption, on the other hand, is a function of the clock speed (speed of transistor switching) and the transistor's capacitive loading. It again depends on the physical transistor geometry. More specifically, we see that I = C dV/dt and PD = ID Vcc = C f Vcc2, where C is the capacitive (transistor and wire) load, f is the switching frequency and Vcc is the supply voltage. Ideally, the static power consumption is zero and thus the total power consumption is PD.
Figure 2 shows the leakage and dynamic currents through a CMOS inverter. With advanced process technology nodes, static power consumption is increasing faster than dynamic power consumption.
Figure 2: CMOS inverter with capacitive load
As structure sizes decrease and field strengths within the element generally go up, designers generally adjust the operating voltage to reduce the dynamic power consumption. But the static power draw becomes more of a factor, increasing exponentially with leakage current. Moreover, the sub-threshold leakage current also increases exponentially with temperature.
And the increase in static power consumption is causing more concern. That's because static power consumption affects the total active die and power densities, and increases the risk for hot spots. Managing both static and dynamic power consumption without adversely affecting performance thus requires a certain degree of intelligence and adaptability at both the chip and system level.
|
