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It used to be fairly simple to estimate semiconductor temperature rise. You would just figure out the power dissipated in the component and use a cooling circuit's electrical analogue to figure out what kind of heat sink was needed. Now, however, the problem has been complicated by the strong desire to eliminate heat sinks for size and cost reasons. Semiconductors mounted in thermally enhanced packages require the circuit board to function as the heat sink and provide all necessary cooling. As shown in Figure 1, heat flows through a metal mounting tab and package leading into the printed wiring board (PWB). The heat then flows laterally though PWB traces and through the surface of the board by natural convection to the ambient. The significant factors influencing the die temperature rise are the amount of copper in the PWB and the surface area available for convection heat transfer.
Figure 1: Heat spreads laterally and then from PWB surface to ambient.
(Click this image to view a larger, more detailed version)
Semiconductor datasheets usually give a thermal resistance from the junction to the ambient for a certain PWB configuration. The implication is that the designer just needs to multiply the power dissipation by this thermal resistance to calculate the temperature rise. However, problems arise if your design does not have the specified configuration, or if you need to further reduce the thermal resistance.
Figure 2 presents a simplified electrical analog of the heat flow problem that provides further insight. The power in the IC is represented by a current source and the thermal resistances are represented by resistors. This circuit can be solved for the voltages, which provide an analogue of the temperatures. There is a thermal resistance from the junction to mounting surface, and then a ladder network of lateral resistances through the board and resistances from the board surface to ambient. This model makes the assumptions that 1) the board is mounted vertically, 2) there is no forced convection or radiation cooling, all heat flow occurs through the copper within the board; and 3) that there is little temperature differential between both sides of the board.
Figure 2: Electrical equivalent of heat flow simplifies temperature rise estimation.
(Click this image to view a larger, more detailed version)
Figure 3 shows the impact of increasing the amount of copper in the PWB to improve the thermal resistance. A factor of three improvement is possible when going from 1.4 mils copper (two-sided, half-ounce) to 8.4 mils (4 layers, 1.5 ounce). Two curves are presented: one for a small package where the heat flow into the board occurs in a 0.2 inch diameter; and a larger part where the heat flows into a 0.4 inch diameter. Both are for a nine-square-inch PWB. These curves correlate quite well with published data and can be useful to estimate the impact of varying the board construction from the data sheet. However, be careful using this information. It assumes no other power dissipation within the nine-square-inches of PWB, which may not be the case.
Figure 2: Electrical equivalent of heat flow simplifies temperature rise estimation.
(Click this image to view a larger, more detailed version)
Please join me next month when we will discuss estimating transient load response.
References
"Power Supply Layout Considerations," R. Kollman, TI Unitrode Power Supply Seminar, SEM1600, Topic 4, 2004-5:
http://focus.ti.com/docs/training/catalog/events/event.jhtml?sku=SEM405006
"Power Pad Thermally Enhanced Package " SLMA002D," by Steven Kummerl, Texas Instruments, October 2008:
http://focus.ti.com/general/docs/techdocsabstract.tsp?abstractName=slma002d
The Power Tips! series
#1, July 2008: Picking the right operating frequency for your power supply
#2, August 2008: Taming a noisy power supply
#3, September 2008: Damping the input filter --- Part 1
#4, October 2008: Damping the input filter --- Part 2
#5, November 2008: Buck-boost design uses a buck controller
#6, December 2008: Accurately Measuring Power Supply Ripple
#7, January 2009: Efficiently driving LEDs offline
#8, February 2009: Reduce EMI by varying power supply frequency
 Robert Kollman is a Senior Applications Manager and Distinguished Member of Technical Staff at Texas Instruments. He has more than 30 years of experience in the power electronics business and has designed magnetics for power electronics ranging from sub-watt to sub-megawatt with operating frequencies into the megahertz range. Robert earned a BSEE from Texas A&M University, and a MSEE from Southern Methodist University.
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