Clock mesh variation robustness: benefits and analysis

Circuit delay is increasingly affected by process variations at lower technology nodes.

Variations in the manufacturing process may cause two gates that are electrically identical and in close proximity to significantly vary in delay. Consequently, designers add significant timing margin to safeguard their designs against timing violations.

Clock mesh technology provides uniform, low skew clock distribution and offers better tolerance to on-chip variations (OCV) than conventional clock tree technology. The need to control OCV effects is now driving clock mesh technology to mainstream designs.

This article gives an overview and highlights the benefits of clock mesh technology compared to conventional clock tree methods.

TECH PAPER
1. Advanced Verification of Low Power Designs

TECH PAPER
2. Low-Power Physical Design with Olympus-SoC

TECH PAPER
3. Advanced Dynamic Power Reduction Techniques: Operand Isolation, Operand Pre-computation, and Multi-V_DD

TECH PAPER
4. Establishing Confidence in PDN Simulation