In a well-orchestrated and clearly scripted show of force, the CEOs of the three "largest" companies in EDA appeared together under the Big Top at the 2009 Design Automation Conference in San Francisco on Monday, July 27th, for a highly touted afternoon keynote panel purportedly addressing "Futures for EDA."
There was only one problem with the event: The CEO of the single largest company in EDA was not actually there. Given that TSMC is listed more than any other company on the roster of exhibitors at DAC 2009, 13 different times, TSMC CEO Morris Chang should, in fact, have been seated on stage, side-by-side with Synopsys CEO Aart de Geus, Mentor Graphics CEO Wally Rhines, and Cadence CEO Lip-Bu Tan.
However, neither Chang's absence, nor TSMC's continued reluctance to acknowledge their role as an EDA company changes an emerging reality within the EDA ecosystem. With each passing year, TSMC wields more and more power. Here in 2009, that power has reached a critical mass, so much so that TSMC is now really more than just an EDA company; it's an entire EDA ecosystem unto itself.
In April of this year, TSMC announced an "Integrated Sign-off Flow" for 65-nanometer digital designs, described as "an automated RTL-to-GDSII chip implementation flow that tightly integrates all process-specific items including pre-qualified libraries and IP, selected EDA tools, production quality flow, advanced design methodology, and TSMC foundry technology files." The only pieces missing in this laundry list of glue and capabilities are the design tools themselves.
In April, as well, the company announced its first "Mixed Signal/RF Reference Design Kit," also for 65 nanometers, to meet the needs of custom designs.
In May, the company announced its iRCX "interoperable" EDA data format for both 65- and 40-nanometer designs, which the company said "unifies interconnect modeling data delivery."
Here in July at DAC, TSMC announced its iPDK, an "interoperable" process design kit validated at 65 nanometers, as well as its iDRC and iLVS, "interoperable" design rule check and "interoperable" layout-versus-schematic data formats, both validated at 40 nanomters.
Meanwhile, and per usual, TSMC took advantage of DAC 2009 to announce its latest approved tool flow, Reference Flow 10.0, which certifies tools from Altos, Anova, Apache, Azuro, Cadence, CLK DA, Extreme DA, Magma, Mentor, Nannor, and Synopsys.
With these various announcements over the last several months, TSMC has become iTSMC, operating under the auspices of the company's new umbrella concept, the Open Innovation Platform, which cleverly takes the "Common" out of Common Platform and swaps in "Open Innovation" instead. (After all, wouldn't you rather be associated with something that has both "Open" and "Innovation" in its name, rather than something that's just "Common"?) To celebrate the new platform, TSMC is hosting what is, in effect, a mini-DAC in San Francisco right in the midst of traditional DAC.
Residing within TSMC's Open Innovation Forum Booth (read, "Gated Community"), are 12 smaller booths representing the 4 large EDA vendors (Synopsys, Cadence, Mentor Graphics, and Magma), 4 smaller EDA vendors (SpringSoft, Integrand, Lorentz, and Tela Innovations), 2 design-services organizations (Global UniChip and Wipro), and an IP vendor, Virage Logic.
The fact that some of these companies are hosting separate booths out on the traditional exhibition hall floor is of no concern. In fact, despite the square footage dedicated to the TSMC Open Innovation Forum Booth in the South Hall at Moscone Center in San Francisco, TSMC itself has an additional booth in the North Hall, as well, which begs the question: Can there ever be too much of a good thing? It begs other questions as well.
Is all of this the beginning of a beautiful friendship between TSMC and everybody else in EDA? Will other companies be allowed into the Gated Community at next year's DAC in Anaheim?
Will TSMC soon become a full-fledged member of EDAC? Will Wally Rhines and Aart de Geus finally be relieved of the endless round-robin responsibility of chairing EDAC, stepping aside so Morris Chang can shoulder that burden for a while?
Will the major EDA vendors abandon efforts to meet the demands of other fabs in the industry, ceeding to TSMC the role of de-facto industry standard in all areas related to manufacturing? Will the Common Platform succumb to the charms of the Open Innovation Platform?
It's not clear that these questions have answers. It's not even clear if these are the right questions. The only thing that is clear is that somewhere over the last few years, the influence of TSMC within the EDA industry has become ubiquitous, with the TSMC Tsunami at DAC a reflection of that reality.
The next time the CEOs of the three "largest" companies in EDA get together for a panel under the Big Top to talk about Futures in EDA, let's hope that they actually talk about the tsunami in the room. Let's hope they talk about the one company that currently seems to hold the future of EDA in the palm of its hand. Let's hope they talk about TSMC.
