October 21, 2005

Get accurate current measurements to your controller with a maximum duty cycle clamp

By John Bottrill, Senior Applications Engineer, Texas Instruments

Today, regulatory agencies (EN/IEC61000-3-2) have legislation requiring units that draw power over 75 watts have a specified-level of harmonic content. This legislation was enacted to allow the maximum power to be transmitted over the power lines and to limit the harmonic content on these lines. The best method of meeting this requirement is having the current drawn from a power line closely following the shape of the incoming voltage. To meet these objectives, the use of a Power Factor Correction (PFC) circuit, which actively forces the input current to follow the line’s voltage, is one of the most desirable options. These circuits are quite complex in nature.

To accomplish this function of the PFC requires that the current be measured and be presented to the controller IC. In the higher power units this means large input currents. Since the currents are quite large, any voltage across a sense resistor will result in large power losses in the sense resistor. To avoid this, a current sense transformer is often used. This is put in series with the switch that is controlled by the PFC controller and can measure the current very accurately without dissipating much power. However there is a problem with this method of measuring the current when the controller demands duty cycles that approach 100%. Since the current transformer is a magnetic device the volts/seconds integral across the transformer over several cycles must sum to zero. Because of the inherent parasitic elements in the current transformer, it may not be able to reset (sum to zero) with very short off times. When this happens the transformer tends to walk up the magnetic flux curve and approach saturation. If this occurs, the information that the transformer is presenting to the controller becomes corrupted and can result in circuit failure. For this reason a maximum duty cycle clamp may be needed

PWM (pulse width modulated) converters, of which a PFC is one type, operate by turning a switch on and off with a controlled duty cycle. During the on time, energy is stored in a magnetic device and then during the off time, the magnetic device releases that energy.

The ratio of the maximum on time to the minimum off time is often controlled by the clock which is a ramp generator in most systems. The maximum on time is usually the time it takes to charge a capacitor with a voltage ramp and the minimum off time is the time it takes to discharge the ramp voltage. In the case of the UCC3817 these currents are set by two current sources controlled by a single resistor. The discharge current is designed to be a factor of 19 times the charge current.

In a PFC controller the duty cycle required for operation without distortion often approaches 100% so a 19 to 1 duty factor though it appears high is reasonable and if the current sensing is done resistively it is. If the current sensing is done with a current transformer and the frequency is high the current transformer may not be able to reset at maximum duty cycle.

The solution to this problem is to increase the mandatory off time which can be done by increasing the fall time of the ramp voltage thus insuring that the current transformer has sufficient time to reset. This may result in slightly higher crossover distortion but it should be acceptable.

Figure 1. Circuit A

Figure 2. Circuit B

Circuit A (Figure 1) consist of three additional components. These are QA1, DA1, and CTA2. The original circuit remains as it was originally designed with the possibility of reducing Rt (not shown) by a factor of 5%. During the positive ramp portion, the transistor QA1 charges the added capacitor CTA2 at the same rate as the IC is charging the capacitor CT but to a voltage level one Vbe below the original CT. Because of the transistors gain the charge time of the ramp will remain the same (within about 1%).

When the voltage on the CT pin reaches the peak and then starts to fall, it will fall at its normal rate (the rate that it fell before the addition of this circuit) until the voltage on CT drops by a Vbe plus a diode drop. At this point the current drawn by the current source in the IC will start to be drawn from both CT and CTA2. The new dv/dt on the CT pin after the initial drop will be the result of the two capacitors being discharged by the fixed value current source. If the second capacitor is the same as the old the ratio of the new off time to the old will be approximately double assuming that the ramp peak to peak voltage is high enough to make the diode and Vbe drops comparatively small.

A more exact method of finding the capacitor from the new fall time:
T2 is CTA2 = ((T2-T1)*CT *Vpp)/((Vpp-2*Vbe)*T1)
where Vpp is the ramp peak to peak voltage, CT is the initial capacitor, and T1 is the initial fall time.

The other factor that will shift is the frequency as the up slope does not change; the down slope will be extended. Since this will be approximately a 5% overall frequency shift the Rt resistor can be reduced by the same percentage to achieve the old desired frequency.

The effect of adding Circuit A can be seen in the difference between Figure 3 and Figure 4, where Figure 3 is the waveform for the circuit before the additional components are added and Figure 4 shows the effect of the modification. In this case the capacitor added was the same size as the one already in the circuit. Figures 3a and 4a show the same waveforms but in addition it shows the circuit generating a maximum duty cycle pulse and how much that pulse is changed by the change in the fall time. It also shows a change in the frequency by 6% in this case.

Figure 3. Unmodified Waveforms

Figure 4. Circuit A added to circuit

Figure 3a. Unmodified with gate drive

Figure 4a. Modified with gate drive

Because nothing has happened to the peak and valley of the ramp and the charge ramp is still linear the calculations of the control loop gain will still apply.

The difference in the down slope is shown in the waveforms of Figure 5 and Figure 6. Figures 5A and 6A show the maximum duty cycle pulse and focus on the increase in the “off time”.

Figure 5. Unmodified Waveforms

Figure 6. Modified waveform with circuit A

Figure 5a. Unmodified showing max duty

Figure 6a. Modified showing max duty

There was some concern about the possibility of oscillation of the circuit due to the negative impedance aspect of the emitter resistance however these were investigated and are not considered to be significant.

Circuit B shown in Figure 2 consists of 2 additional components transistor QB1 and resistor RB1. During the charge cycle the current out of the CT pin charges the capacitor CTB through RB1 which is relatively small and so has little or no impact on the charge cycle.

When the voltage reaches its peak and the CT pin starts to pull current out of the capacitor through RB1 and out of the transistor. The current out of the capacitor is limited by the resistor RB1 and the Vbe of the transistor. When the voltage across the resistor RB1 reaches the Vbe of the transistor QB1, the transistor is turned on in the active region and provides any additional current that the CT pin is calling for.

The capacitor will be discharged at a linear rate by a current of Vbe/RB1 until the minimum voltage is reached at the CT pin and the discharge cycle ends. By selecting the value of RB1, the rate of the discharge can be set.

The things that have to be remembered is that the CT voltage will immediately drop by one Vbe as the peak voltage is reached and that there will still be one Vbe of voltage above the minimum ramp valley left on the capacitor when the discharge cycle stops.

Figure 7 shows the voltage waveform before the change of the timing components for the B circuit and Figure 8 shows the waveform of the timing circuit after modification to make it circuit B.

Figure 7. Before change

Figure 8. Discharge waveform of Circuit B

During operation at the valley of the ramp waveform the currents direction is reversed and the voltage on the CT pin immediately jumps to one Vbe plus the resistance RB1 times the charge current above the voltage where the ramp valley was set. Since the charging current is small the voltage across RB1 can be neglected.

The effect of this is two fold. The frequency of operation is significantly changed because of the effective change in the ramp amplitude (the peak to peak amplitude is decreased by a Vbe). This can be seen in the above figures where the frequency increased by 10% even though the down ramp increases in time by about 6% of the total time (See Figures 9 and 10).

Figure 9. Down slope before

Figure 10. Down slope after Circuit B

Increasing the down time by a factor of two would result in approximately a 5% variation in the frequency however the variation in the up ramp will be more significant. In this case with a ramp of 4.2 volts the ramp up slope will be decreased by about 15% (one Vbe) causing an increase in frequency of about 10% total because of the 5% increase in the discharge time. Thermal effects on frequency will be higher on this circuit than on circuit A as Vbe will affect the effective range of the ramp during the charge slope which is shallow compared to the down slope.

The second thing is the change in the effective amplitude of the ramp. As can be seen in Figures 7 and 8 even though the ramp and valley trip points remain the same the effective ramp is decreased by the amount of the step function at the beginning of the each cycle (one Vbe). The gain equation should be revisited with the new peak to peak amplitude in mind.

In the gain equation it will have a small but significant effect as the ramp amplitude is a factor in the equation and it will be reduced by about 16%

Conclusion:
There are two circuits presented to achieve an increase in the minimum “off time” of the power switches. This may be needed to allow the current transformers used in some circuits to reset and prevent catastrophic failure.

My thanks to SAE Power for their contributions of Circuit B for this paper.

Author Info:
John Bottrill is a Senior Applications Engineer for Texas Instruments in the Power Converter Products group. He earned his BSEE at Queen's University, Kingston, in Ontario, Canada.john_bottrill@ti.com