November 27, 2005

Chip-scale packaging comes of age for power devices

By Dave Heacock, Vice President of Portable Power Management, Texas Instruments

The benefits of chip-scale packages are fairly obvious. In space-constrained, very dense designs, every bit of board space is precious. Chip-scale packaging, which eliminates the extra space along the sides of conventional device packages devoted to wire leads, saves valuable board space for other critical on-board functionality. With a chip-scale package, the silicon die is attached directly to the circuit board by solder bumps underneath the die.

But everything comes with trade-offs and "the rap" on chip-scale packaging is that it creates additional assembly and manufacturing difficulties and raises some board-level reliability issues. In certain applications and types of devices, the benefits of space-saving chip-scale packages have been enough to overcome any trade-offs. Now, from the industry's more than ten years of experience with bumped packages like ball grid arrays (BGA) and flip chips, chip-scale has arrived for a wide variety of power devices.

Driven by demand

One only needs to pick-up a smartphone, personal digital assistant (PDA) or a slim laptop computer to realize that space-saving packaging is very desirable for many popular applications. In portable or hand-held systems, board space "real estate" is highly-valued. If most system designers could, they would probably devote most of the board space to functionality because that's what sets their products apart in the marketplace. While power devices are essential to enabling that functionality, power is not the system's primary function and board space allocated to it is scrutinized conspicuously.

Space-saving concerns are also intruding on more traditional applications where the PCB footprint of many devices has not been a major issue. For example, a new compact-type of desktop personal computer is growing in popularity. Called a portable desktop, the system enclosure is small and unobtrusive and provides "a clean-and-uncluttered" desktop. Sometimes the computer is so small that it can be hidden inside the monitor's base.

In the future, the trend toward miniaturization will continue to touch a wider range of applications throughout the computer, communications and electronics industry. So in general, the increasing demands for smaller chip-scale packaging in power devices as well as other types of semiconductors will continue.

The packaging cycle

New, innovative types of packages typically follow some type of adoption trajectory. For example, when surface-mount packaging was introduced more than 20 years ago there was industry "resistance." The performance of surface-mount packaging had to be fully-evaluated and analyzed before adoption could be contemplated. New handling and assembly equipment had to be installed and brought up-to-speed. And even after these hurdles had been crossed, only the applications that most needed the advantages of surface-mount packaging embraced the new packaging in a big way. As time went by and surface-mount proved its worth, it was adopted throughout the industry in practically every type of application and for most types of semiconductor devices.

Similarly for power devices, when leadless packages like the QFN [quad flat no-leads package] were introduced several years ago. They were accepted in many applications. However, QFN packages also met with some resistance since a new package means changes in manufacturing. The same is happening with chip-scale power devices. Once manufacturers realize the benefits associated with chip-scale packaging, the adoption cycle will accelerate.

Based on a decade's worth of experience, many of the trade-offs that were initially ascribed to chip-scale packaging have been overcome. In some instances, this has been achieved by creative solutions; in others, the performance of the packaging itself has won over the skeptics.

For example, the thermal-cycle performance of chip-scale packages was considered worse than traditional packaged devices. Many applications that could benefit from chip-scale packages were delayed because of this short coming. Through the use of better materials such as a polyimide layer, thermal cycle performance has improved to a level achieved by traditionally packaged devices.

With regards to power products, power dissipation and changes in lead inductance become an issue. Without the benefit of a large power-pad area around the die, how can heat be dissipated effectively? By using bump contacts over the critical power areas, thermal dissipation of chip-scale packaged devices can approach that of thermally- enhanced traditional packaging methods. With the elimination of wire bonds on the switching outputs, higher PWM switching frequencies are achieved with chip-scale products. This could lead to smaller inductor sizes, and reduction in the overall system solution for power rails.

In addition, implementing smaller power devices in chip-scale packages "frees up" extra board space that might be needed for a larger microprocessor capable of supporting additional features and functionality.

Of course, the higher power efficiencies of chip-scale packages is particularly important in portable battery-powered applications where greater power efficiency leads to longer battery life and stand-by times.

Board-level issues

Power devices in chip-scale packaging offer several positive advantages for circuit board designers. And as for any trade-offs of chip-scale packaging, creative solutions have been developed over the years to address them.

For example, the planarity of chip-scale packaging is an improvement over older packaging types. With no leads to bend, rework is reduced for chip-scale packages. Another example is the PCB routing. With bumps located across the surface of the chip-scale package, many times a higher-routing density can be achieved compared to traditional package types. With the die-size now driving the package size, the minimum space for a particular power function is achieved. Figure 1 compares the effective PCB reduction for chip-scale packages compared to other package types of a 208 I/O 7.6mm² die.

Package Type   Pitch   Max. Package Dimension   Area   PQFP   0.5mm   31mm   100%  PBGA   1.27 mm   23mm   55%  COB   0.23mm   19mm   38%  CSP   0.5mm   8mm   7%  WCSP   0.5mm   7.6mm   6%

Figure 1: The effective PCB reduction for chip-scale packages compared to other package types

Several other board-level reliability issues come up with regards to chip-scale packaging. Moisture can penetrate the die in a chip-scale package, for example, to possibly corrode the contact points, or metal, on the die’s bottom-side. Epoxy conformal coatings can be used to seal out moisture and block out any contaminant, but this is expensive. Today, most chip-scale packages are designed to "pass" moisture testing and eliminate the need for underfill, or conformal coating. Light can be an issue with expose of a bare die in chip-scale packages. A silicon die can act as a photo detector when it is exposed to light sources causing a change in the state of the circuit. This phenomenon is more often encountered in analog circuits, but it can be overcome with a protective coating that shields chip-scale devices from light.

Chip-outs on the die edge, covered by traditional packaging techniques are now exposed with chip-scale packages. Methods such as improved the wafer sawing, and better edge polyimide sealing eliminates this largely cosmetic issue. Board-level reliability testing is necessary to alleviate these concerns.

Manufacturing trade-offs

Anytime a new and innovative package type comes on the scene there are trade-offs in manufacturing operations. Often, these manufacturing changes involve new handling, assembly or other sorts of equipment and that means a capital investment. Most capital expenditures are only made when the firm is certain of a fast return on its investment (ROI). Chip-scale packaging for power devices has certainly reached that point for many end-equipment manufacturing operations.

With more than 10 years of experience with bumped packages, most notably BGAs, manufacturing equipment suppliers have improved their machinery greatly. Much of this equipment has been re-designed so that it can handle the greater precision required by the smaller chip-scale packages. Many times this modern manufacturing equipment for chip-scale devices can actually achieve faster throughput than traditional machines, and require less floor space. The result is an accelerated ROI on chip-scale manufacturing equipment.

Of course, chip-scale packages can require changes in manufacturing test processes too. With the higher-packaging density on the board, test pads are disappearing from densely populated circuit boards. New test technologies such as boundary scan (IEEE 1149.1/JTAG) are increasing in importance. Optical and x-ray inspection systems are being deployed to locate manufacturing faults. By using a combination of new test technologies, board-level test coverage can be improved over older more traditional test methods.

Re-work and repair operations are somewhat challenged by the use of chip-scale packages because the die and its small contacts. A higher level of manufacturing precision is needed to eliminate PCB rework since rework may be impractical for boards utilizing chip-scale packages.

Benefits "tip the scales"

The challenges and care demanded by power devices in chip-scale packages are far outweighed by the many benefits this small, compact package has to offer. The chip-scale's smaller implementation size, improving thermal characteristics and board-level reliability will contribute to its rapid adoption in power devices. Moreover, much has been learned during the last 10 years about designing and manufacturing circuit boards with chip-scale devices. In the final analysis, the many positives associated with chip-scale packaging technology make it a natural selection for power devices.

Author info
Dave Heacock is the vice-president of Portable Power Management at Texas Instruments. You can contact him at: dheacock@list.ti.com